A typical capacitive gain amplifier chops an input signal by alternating between two chopping (CHP) amplify phases with the second CHP phase having a polarity of the amplified signal inverted compared to the first CHP phase. The output of the capacitive gain amplifier circuit may be input to an analog to digital converter (ADC) circuit to be converted from analog to digital. Accuracy of conversion improves when the final voltage of the output from the capacitive gain amplifier circuit is well settled to the correct final value before the ADC circuit takes a sample for conversion. It is thus desirable for high frequency periodic sampling of signals that the capacitive gain amplifier circuit settle its output voltage to an accurate final value rapidly. A maximum sampling rate or frequency of the capacitive gain amplifier circuit is limited by how quickly the amplified sample values settle to an accurate final value.
Miller capacitors are placed across the differential amplifiers of a capacitive gain amplifier circuit from the input to the output in order to stabilize the amplifiers. A Miller capacitor's capacitance value is recognized as a different value of capacitance at the amplifier's input and output nodes than the face value of the capacitor according to the Miller effect. The Miller capacitor adds a dominant left-half plane pole to the frequency response of the amplifier according to its Miller capacitance to stabilize or compensate the amplifier. However, slewing of the Miller capacitor during chopping between the two CHP phases in a conventional capacitive gain amplifier may limit its speed of operation.